This application claims priority from Korean patent application No. 98-21235 filed Jun. 9, 1998 in the name of Samsung Electronics Co., Ltd., which is incorporated by reference.
1. Field of the Invention
The present invention relates generally to voltage boosting circuits, and more particularly, to power supply voltage boosting circuits having cross-coupled precharge circuits.
2. Description of the Related Art
Signals in dynamic random access memories (DRAMs) constructed using CMOS transistor technology experience a voltage drop of somewhat more than the threshold voltage of a MOS transistor while being transmitted through the channel region of the MOS transistor. Such voltage drops can cause information loss and interfere with data read and write operations.
Continuous increases in the density and capacity of semiconductor memory devices have caused a commensurate increase of power consumption. Therefore, semiconductor memory devices use internal power supply voltages to reduce power consumption and enhance reliability.
To correctly read and write data from or to a memory cell composed of a MOS transistor and a capacitor, a voltage sufficient to overcome the threshold voltage of the MOS transistor must be provided. For example, the internal power supply voltage is typically boosted by 1.5V to drive word lines that are connected to the gates of the MOS transistors.
FIG. 1 is a block diagram of a conventional power supply voltage boosting circuit, and FIG. 2 is a circuit diagram showing more details of the circuit of FIG. 1.
Referring to FIG. 1, the power supply voltage boosting circuit shown generally at 1 generates a boosted voltage Vpp which is higher than a power supply voltage (for example the internal power supply voltage Vcc) and includes a detector 12, oscillator 14, first and second drivers 16 and 22, first and second pumping circuits 18 and 24 (also referred to as main pumping circuits), and first and second precharge circuits 20 and 26.
Detector 12, which detects whether the voltage Vpp is higher than a predetermined target voltage level, is coupled to a power line 10 which transfers the voltage Vpp to other circuits. Detector 12 generates a signal DET which goes low to disable the oscillator 14 when Vpp is higher than the target level. When Vpp is lower than the target level, detector 12 drives the signal DET to a logic high level to enable the oscillator. As shown in FIG. 2, detector 12 includes to resistors R1 and R2 coupled in series between the power line 10 and a power supply ground terminal. An inverter INV11 has in input terminal connected to the node between R1 and R2 and an output terminal for generating the signal DET.
Referring again to FIG. 1, oscillator 14 generates an oscillation signal OSC which is enabled or disabled in response to the detection signal DET. When DET is high, the oscillator 14 outputs the oscillation signal OSC which oscillates with a predetermined period. When DET is low, the oscillation signal OSC is disabled and remains, for example, at a logic high level. As shown in FIG. 2, oscillator 14 includes a 2-input NAND gate G1 and two series connected inverters INV2 and INV3. Refening again to FIG. 1, the first driver 16, the first pumping circuit 18 and the first precharge circuit 20 form a first boosted voltage generating section which performs a pumping operation to raise the potential of power line 10 during a first half period of the oscillation signal OSC. As shown in FIG. 2, the first driver 16 includes 3 series connected inverters INV6, INV7 and INV8, which receive the oscillating signal OSC and output a first signal .phi.1.
The first pumping circuit 18 includes a pumping capacitor C2 and two NMOS transistors M3 and M4. Transistor M3 is diode-connected between Vcc and a pumping node N2, and M4 is diode-connected between node N2 and the power line 10. Capacitor C2 is connected between the output of the first driver 16 and the gate of M4 at node N2. The first precharge circuit 20 includes two inverters INV4 and INV5, a pumping capacitor C1, and two NMOS transistors M1 and M2. Inverters INV4 and INV5 are connected in series to generate a second signal .phi.2 in response to OSC. Transistor M1 is diode-connected between Vcc and a pumping node N1, while M2 is diode-connected between nodes N1 and N2. Capacitor C1 is connected between the gate of M2 at node N1 and the output of INV5 to receive the signal .phi.2.
Referring back to FIG. 1, the second driver 22, the second pumping circuit 24, and the second precharge circuit 26 form a second boosted voltage generating section which performs a pumping operation to raise the potential of power line 10 during a second half period of the oscillation signal OSC. As shown in FIG. 2, the constituent components of the second boosted voltage generating section are essentially identical to those of the first section, with pumping nodes N3 and N4 corresponding to pumping nodes N1 and N2, respectively, and signals .phi.2B and .phi.1B corresponding to signals .phi.1 and .phi.2, respectively. However, the second precharge circuit 26 and the second driver 22 are driven by a second oscillating signal OSCB which is complement of OSC and is obtained through inverter INV9. Because the two sections operate during alternate half cycles of the oscillation signal OSC, two pumping operations are performed during each cycle of OSC.
The operation of the power supply voltage boosting circuit 1 will now be described more thoroughly with reference to FIGS. 1 and 2.
When the oscillation signal OSC switches from a high to a logic low level, capacitor C1 in the first precharge circuit 20 performs a negative pumping operation so that node N1 is charged to a voltage of VCC-Vtn via the transistor M1 (where Vtn represents a threshold voltage of an N-type MOS transistor). Since the output signal .phi.1 from the first driver 16 switches to a logic high level, node N2 in the first pumping circuit 18 is boosted to 2VCC-Vtn via capacitor C2.
At the same time, since the output signal .phi.1B from the second driver 22 switches to a logic low level, capacitor C4 in the second pumping circuit 24 performs a negative pumping operation so that node N4 is charged to a voltage of VCC-Vtn via the NMOS transistor M7. Node N3 in the second precharge circuit 26 is boosted to 2VCC-Vtn by the capacitor C3, so that node N4 is then precharged to a voltage of 2VCC-2Vtn. Hereinafter, the above described operation is referred to as "a precharge pumping operation".
When the oscillation signal OSC switches from a low to a logic high level, the power line 10 is boosted to 3VCC-3Vtn by the second pumping circuit 24, and node N2 is precharged to a voltage of 2VCC-2Vtn through the first precharge circuit 20.
More specifically, at the low-to-high transition of OSC, the signal .phi.1B from the second driver 22 goes high, so node N4 is boosted to 3VCC-2Vth via capacitor C4. Therefore, the power line 10 is boosted to 3VCC-3Vtn through NMOS transistor M8 (hereinafter, the above described operation is referred to as "a main pumping operation"). Capacitor C3 performs a negative pumping operation, so node N3 is charged to a voltage of VCC-Vtn. At the same time, capacitor C2 in the first pumping circuit 18 performs a negative pumping operation because the signal .phi.1 from the first driver 16 switches to a logic low level. Capacitor C1 pumps node N1 in the first precharge circuit 20 to a voltage of 2VCC-Vtn in response to the signal .phi.2 from the invertor INV5 so that node N4 is precharged to a voltage of 2VCC-2Vtn. That is, the precharge pumping operation is performed.
As described above, at the low-to-high transition of the oscillation signal OSC, the precharge pumping operation for node N2 is performed while the second pumping circuit 24 performs the main pumping operation. On the other hand, at the high-to-low transition of the oscillation signal OSC, the precharge pumping operation for node N4 is performed while the first pumping circuit 18 performs the main pumping operation. Therefore, according to the above described boosting circuit structure, it is possible to speed up the pumping operation because the two pumping operations are performed during alternate half-cycles of the oscillation signal OSC.
However, the threshold voltage drops of the NMOS transistors M1 and M5 in the first and second precharge circuits 20 and 26 reduce the pumping efficiency. That is, since node N1 is charged to a voltage of VCC-Vtn before the precharge pumping operation, node N2 has a voltage of 2VCC-2Vtn after the precharge pumping operation. Therefore, when the main pumping operation is performed, the voltage Vpp on the power line 10 is only pumped to 3VCC-3Vtn. If the power supply voltage VCC is about 2 volts and the threshold voltage Vtn is about 1 volt, the voltage Vpp on the power line 10 is only pumped to about 3 volts (3.times.2volts-3.times.1 volt) which is inadequate to sufficiently turn on a memory cell transistor when it is applied to the gate of the transistor. As a result, the circuit 1 illustrated in FIG. 2 has a low pumping efficiency. Furthermore, if the power supply voltage VCC is reduced, the pumping efficiency of the circuit of FIG. 2 becomes even lower due to the threshold voltage drops of the transistors M1 and M5.